Write-driver circuit

ABSTRACT

In a write driver circuit for switching the direction of a write current passing through a magnetic head or the like having an inductance component, an H-shaped bridge circuit is formed by using four NPN transistors in order to switch the write current at a high speed. Four switching means for controlling the base potentials of the four NPN transistors are provided and two switching means for rapidly decreasing the base potential of one of the two NPN transistors on the power source side, which is turned off when the write current passing through the magnetic head is switched are provided, thereby widening a voltage difference occurring between both terminals of the magnetic head.

TECHNICAL FIELD

The present invention relates to a write driver circuit for recording adigital signal onto a magnetic recording medium by using a magnetic headhaving an inductance component, which is built in, for example, amagnetic disk apparatus or the like.

BACKGROUND ART

A conventional write driver circuit will be described with reference toFIG. 9. In the write driver circuit, as illustrated in FIG. 9, thecollectors of NPN transistors Q21 and Q22 are connected to a power inputterminal (Vcc), the collector of an NPN transistor Q23 is connected tothe emitter of the NPN transistor Q21, the collector of an NPNtransistor Q24 is connected to the emitter of the NPN transistor Q22,the emitters of the NPN transistors Q23 and Q24 are connected to eachother, and a current source I1 is connected between the emitters of theNPN transistors Q23 and Q24 and the ground terminal.

A resistor R25 is connected between the collector and base of the NPNtransistor Q21, a resistor R26 is connected between the collector andbase of the NPN transistor Q22, the collector of an NPN transistor Q25is connected to the base of the NPN transistor Q21, the collector of anNPN transistor Q26 is connected to the base of the NPN transistor Q22,the emitters of the NPN transistors Q25 and Q26 are connected to eachother, and a current source I2 is connected between the emitters of theNPN transistors Q25 and Q26 and the ground terminal.

The bases of the NPN transistors Q23 and Q25 are connected to eachother, the bases of the NPN transistors Q23 and Q25 are provided with aninput terminal WD of a write signal, the bases of the NPN transistorsQ24 and Q26 are connected to each other, and the bases of the NPNtransistors Q24 and Q26 are provided with an input terminal WDB of awrite signal.

In the write driver circuit, one (X) of terminals of a magnetic head HDis connected to the connection point of the NPN transistors Q21 and Q23and the other terminal Y of the magnetic head HD is connected to theconnection point of the NPN transistors Q22 and Q24.

In the write driver circuit having such a construction, write signals ofopposite phases are supplied to the input terminals WD and WDB. Forexample, when a high-level (H) write signal is supplied to the inputterminal WD and a low-level (L) write signal is supplied to the inputterminal WDB, the NPN transistors Q21 and Q24 are turned off, the NPNtransistors Q22 and Q23 are turned on, and a current is passed to themagnetic head HD in the direction from the terminal Y to the terminal X.When the states of the write signals are opposite, the NPN transistorsQ21 and Q24 are turned on, the NPN transistors Q22 and Q23 are turnedoff, and a current is passed to the magnetic head HD in the directionfrom the terminal X to the terminal Y.

The conventional write driver circuit has, however, drawbacks asdescribed hereinbelow caused by the fact that the magnetic head HD hasan inductance. Specifically, a counter electromotive force occurringacross the magnetic head HD when the current passing through themagnetic head HD is reversed is expressed by the following expression(1) where the current passing through the magnetic head HD is i, thecounter electromotive force (voltage across the head terminals)occurring across the magnetic head HD is V, the inductance of themagnetic head HD is L, and t denotes time.

V=L(di/dt)  (1)

From the relation of Expression (1), time required for the currentpassing through the magnetic head HD to be reversed is proportional toeach of the inductance L of the magnetic head HD and the current passingthrough the magnetic head HD and is inversely proportional to thecounter electromotive force V. Consequently, the larger the counterelectromotive force V is, the shorter the time required for the currentpassing through the magnetic head HD to be reversed is, because theenergy accumulated by the inductance L of the magnetic head HD isdischarged in accordance with the product of the level of the counterelectromotive force and time.

The operation in a transition period in which, for example, an H-levelwrite signal is supplied to the input terminal WD in a state where anL-level write signal is supplied to the input terminal WD and an L-levelwrite signal is supplied to the input terminal WDB, the state of thewrite signal is changed to a state in which the H-level write signal issupplied to the input terminal WDB, and the direction of the writecurrent passing through the magnetic head HD is changed from thedirection from the terminal X to the terminal Y to the direction fromthe terminal Y to the terminal X will now be described.

In the write driver circuit, when the state of the write signal isreversed, the H-level write signal is supplied to the input terminal WD,and the L-level write signal is supplied to the input terminal WDB, theNPN transistor Q25 is turned on and a current of the current source I2is passed to the resistor R25, so that the base potential of the NPNtransistor Q21 is decreased from the power source voltage by an amountcorresponding to a voltage drop caused by the resistor R25 and thecurrent source I2. Since the NPN transistor Q21 is not completely turnedoff at this time, that is, remains in the on-state, a voltage Vx at theterminal X of the magnetic head HD is dropped from the base potential ofthe NPN transistor Q21 only by a base-emitter voltage Vbe of the NPNtransistor Q21.

On the other hand, when the NPN transistor Q26 is turned off, the basepotential of the NPN transistor Q22 is pulled up to the power sourcevoltage and the NPN transistor Q22 is turned on. A voltage Vy at theterminal Y of the magnetic head HD is consequently dropped from thepower source voltage only by the base-emitter voltage Vbe of the NPNtransistor Q22.

From the above, when the power voltage is Vcc, the voltage differencebetween the terminals X and Y of the magnetic head HD is expressed bythe following expression (2).

|Vy−Vx|=|(Vcc−Vbe)−(Vcc−I2·R25−Vbe)|=I2·R25  (2)

This similarly applies to the case where the reversing direction of thecurrent passing through the magnetic head HD is opposite and the voltagedifference between the terminals X and Y of the magnetic head HD in thiscase is expressed by the following expression (3).

|Vy−Vx|=|(Vcc−I2·R26−Vbe)−(Vcc−Vbe)|=I2·R26  (3)

As described above, since the voltage difference occurring between theterminals X and Y of the magnetic head HD in a transient period isdetermined by the resistor R25 or R26 and the current source I2, thecounter electromotive force generated by the magnetic head HD isregulated by the voltage difference occurring between the terminals Xand Y of the magnetic head HD.

In order to reverse the current passing through the magnetic head HD athigh speed, it is necessary to widen the voltage difference between theterminals X and Y of the magnetic head HD so that the counterelectromotive force generated by the magnetic head HD is not regulated.For this purpose, it is preferable to widen the voltage differencebetween both terminals of the magnetic head HD by increasing the currentof the current source I2 while not increasing the value of resistance ofeach of the resistors R25 and R26 for the following reason. When thevalue of resistance is increased, the area of the resistance regionbecomes large, so that high packing density cannot be achieved.Moreover, the parasite capacity by the resistance region comes to beunignorable and it causes a slow current reversal.

A state after the reversal of the write current passing through themagnetic head HD from the direction from the terminal X to the terminalY to the direction from the terminal Y to the terminal X is finishedwill now be considered. In this case as well, the high-level writesignal is continuously supplied to the input terminal WD and thelow-level write signal is continuously supplied to the input terminalWDB, the NPN transistors Q21 and Q24 are turned off, the NPN transistorsQ22 and Q23 are turned on, and the direction of the write currentpassing through the magnetic head HD is from the terminal Y to theterminal X.

At this time, the voltage Vy at the terminal Y of the magnetic head HDis dropped from the base potential of the NPN transistor Q22 only by thebase-emitter voltage Vbe of the NPN transistor Q22. The voltageVx at theterminal X of the magnetic head HD is dropped from the voltage Vy at theterminal Y only by an amount of a voltage drop caused by the writecurrent passing through the magnetic head HD and the resistancecomponent of the magnetic head HD.

The voltage drop caused by the write current I1 passing through themagnetic head HD and a resistance component RH of the magnetic head HDis expressed by the following expression (4)

|Vy−Vx|=I1·RH  (4)

This similarly applies to a case where the reversing direction of thewrite current passing through the magnetic head HD is opposite. That is,when the reversal of the write current I1 passing through the magnetichead HD is finished, the voltage difference between both terminals ofthe magnetic head HD is determined only by the write current I1 passingthrough the magnetic head HD and the resistance component RH of themagnetic head and the voltage drop by the resistors R25 and R26 does notexert any influence.

From the above, it is necessary to pass a relatively large current tothe current source I2 in order to reverse the write current passingthrough the magnetic head HD at a high speed. When the reversal of thewrite current passing through the magnetic head HD is finished, however,the relatively large current flowing to the current source I2 becomesuseless.

DISCLOSURE OF INVENTION

The invention is to solve the problems and its object is to provide awrite driver circuit in which a current consumption can be suppressedand, moreover, a write current passing through a magnetic head can bereversed at a high speed.

A write driver circuit according to claim 1 comprises: a reversalswitching circuit having a pair of output terminals connected to bothterminals of a magnetic head, for reversing the direction of a writecurrent passing through the magnetic head in response to reversal of awrite signal; and high-speed reversing means for reversing the writecurrent at a high speed by making a voltage difference between bothterminals of the magnetic head in a period from reversal of the writesignal to reversal of the write current to the magnetic head larger thana voltage difference between both terminals of the magnetic head, whichoccurs only in the reversal switching circuit.

With the construction, since the voltage difference between bothterminals of the magnetic head during the write current to the magnetichead is reversed in accordance with the reversal of the write signal iswidened, the counter electromotive force of the magnetic head when thewrite current is reversed can be increased. Consequently, the energyaccumulated in the magnetic head can be discharged at a high speed andthe write current passing through the magnetic head can be reversed at ahigh speed. Also, after completion of the reversal of the write current,the operation of the high-speed reversing means is finished and astationary state is obtained, so that current consumption can besuppressed.

According to the write driver circuit of claim 2, in the write drivercircuit described in claim 1, the reversal switching circuit isconstructed as follows. That is, the reversal switching circuitcomprises: a first power source side transistor and a first ground sidetransistor which are connected in series in the forward directionbetween a power input terminal and a ground terminal; a second powersource side transistor and a second ground side transistor which areconnected in series in the forward direction between the power inputterminal and the ground terminal; first switching means which isconnected to the base of the first power source side transistor andcontrols the first power source side transistor in response to a writesignal; second switching means which is connected to the base of thesecond power source side transistor and controls the second power sourceside transistor in response to the write signal; third switching meanswhich is connected to the base of the first ground side transistor andcontrols the first ground side transistor in response to the writesignal; and fourth switching means which is connected to the base of thesecond ground side transistor and controls the second ground sidetransistor in response to the write signal. The magnetic head isconnected between a connecting point of the first power source sidetransistor and the first ground side transistor and a connecting pointof the second power source side transistor and the second ground sidetransistor, and the operation of a set of the first and fourth switchingmeans and that of a set of the second and third switching means arereversed in response to reversal of the write signal to thereby reversethe operation of a set of the first power source side transistor and thesecond ground side transistor and that of a set of the second powersource side transistor and the first ground side transistor, therebyreversing the write current passing through the magnetic head.

With the construction, in a manner similar to claim 1, the write currentpassing through the magnetic head can be reversed at a high speed andthe current consumption can be suppressed.

According to the write driver circuit of claim 3, in the write drivercircuit according to claim 2, each of the first and second power sourceside transistors and the first and second ground side transistors is anNPN transistor, the first switching means is connected between a powerinput terminal and the base of the first power source side transistor,the second switching means is connected between the power input terminaland the second power source side transistor, the third switching meansis connected between the base of the first ground side transistor andthe ground terminal, and the fourth switch is connected between the baseof the second ground side transistor and the ground terminal.

With this construction, effects similar to those of claim 2 can beproduced.

According to the write driver circuit of claim 4, in the write drivercircuit according to claim 3, the third switching means has a first NPNswitch transistor whose collector is connected to the base of the firstground side transistor and whose emitter is connected to the groundterminal, and the fourth switching means has a second NPN switchtransistor whose collector is connected to the base of the second groundside transistor and whose emitter is connected to the ground terminal.Seventh switching means for rapidly decreasing the base potential of thefirst NPN switch transistor is provided between the base of the firstNPN switch transistor and the ground terminal, and eighth switchingmeans for rapidly decreasing the base potential of the second NPN switchtransistor is provided between the base of the second NPN switchtransistor and the ground terminal.

With the construction, in addition to effects similar to those of claim3, since the base potentials of the first and second NPN switchtransistors as components of the third and fourth switching means arerapidly decreased by the seventh and eighth switching means, a currentcan be rapidly passed to the first and second ground side transistors.Thus, the write current to the magnetic head can be reversed faster.

According to the write driver circuit of claim 5, in the write drivercircuit according to claim 1, the reversal switching circuit andhigh-speed reversing means are constructed as follows. Specifically, thereversal switching circuit comprises: a first power source sidetransistor and a first ground side transistor which are connected inseries in the forward direction between a power input terminal and aground terminal; a second power source side transistor and a secondground side transistor which are connected in series in the forwarddirection between the power input terminal and the ground terminal;first switching means which is connected to the base of the first powersource side transistor and controls the first power source sidetransistor in response to a write signal; second switching means whichis connected to the base of the second power source side transistor andcontrols the second power source side transistor in response to thewrite signal; third switching means which is connected to the base ofthe first ground side transistor and controls the first ground sidetransistor in response to the write signal; and fourth switching meanswhich is connected to the base of the second ground side transistor andcontrols the second ground side transistor in response to the writesignal. The magnetic head is connected between a connecting point of thefirst power source side transistor and the first ground side transistorand a connecting point of the second power source side transistor andthe second ground side transistor, and the operation of a set of thefirst power source side transistor and the second ground side transistorand that of a set of the second power source side transistor and thefirst ground side transistor are reversed by reversing the operation ofa set of the first and fourth switching means and that of a set of thesecond and third switching means in response to reversal of the writesignal, thereby reversing the write current passing through the magnetichead.

The high speed reversing means comprises fifth and sixth switching meansconnected to the bases of the first and second power source sidetransistors, the base potential of one of the first and second powersource side transistors, which is turned off by the reversal of thewrite signal is selectively rapidly decreased to about the groundpotential and the potential at the connecting point of one of the powersource side transistors, which is turned off by the reversal of thewrite signal and the ground side transistor which is serially connectedto the power source side transistor is decreased, thereby widening thevoltage difference between both terminals of the magnetic head.

With the construction, the base potential of one of the first and secondpower source side transistors, which is turned off by the reversal ofthe write signal is selectively rapidly decreased to about the groundpotential and the potential at the connecting point of one of the powersource side transistors, which is turned off by the reversal of thewrite signal and the ground side transistor which is serially connectedto the power source side transistor is decreased, thereby widening thevoltage difference between both terminals of the magnetic head.Consequently, in a manner similar to claim 2, the write current passingthrough the magnetic head can be reversed at a high speed and thecurrent consumption can be suppressed.

According to the write driver circuit of claim 6, in the write drivercircuit according to claim 5, each of the first and second power sourceside transistors and the first and second ground side transistors is anNPN transistor, the first switching means is connected between a powerinput terminal and the base of the first power source side transistor,the second switching means is connected between the power input terminaland the second power source side transistor, the third switching meansis connected between the base of the first ground side transistor andthe ground terminal, the fourth switch is connected between the base ofthe second ground side transistor and the ground terminal, the fifthswitching means is connected between the base of the first power sourceside transistor and the ground terminal, and the sixth switching meansis connected between the base of the second power source side transistorand the ground terminal.

With the construction, effects similar to those of claim 5 are produced.

According to the write driver circuit of claim 7, in the write drivercircuit according to claim 6, the third switching means has a first NPNswitch transistor whose collector is connected to the base of the firstground side transistor and whose emitter is connected to the groundterminal and the fourth switching means has a second NPN switchtransistor whose collector is connected to the base of the second groundside transistor and whose emitter is connected to the ground terminal.Seventh switching means for rapidly decreasing the base potential of thefirst NPN switch transistor is provided between the base of the firstNPN switch transistor and the ground terminal; and eighth switchingmeans for rapidly decreasing the base potential of the second NPN switchtransistor is provided between the base of the second NPN switchtransistor and the ground terminal.

With the construction, effects similar to those of claim 6 are produced.Moreover, since the base potentials of the first and second NPN switchtransistors as components of the third and fourth switching means arerapidly decreased by the seventh and eighth switching means, a currentcan be rapidly passed to the first and second ground side transistorsand the write current to the magnetic head can be therefore reversedmore rapidly.

According to the write driver circuit of claim 8, in the write drivercircuit according to claim 2, 3, 4, 5, 6, or 7, the third and fourthswitching means control the first and second ground side transistorswithin active regions, respectively.

With the construction, since the first and second ground sidetransistors are controlled within active regions, respectively, thecurrent passed to the first and second ground side transistors can beswitched at a high speed. As a result, the direction of the current tothe magnetic head can be switched more rapidly.

According to the write driver circuit of claim 9, in the write drivercircuit according to claim 2, 3, 4, 5, 6, or 7, each of the first andsecond ground side transistors is an output side transistor of a currentmirror circuit.

With the construction, effects similar to those of claim 2, 3, 4, 5, 6,or 7 are produced. In addition, since the first and second ground sidetransistors also serve as constant current circuits, it is unnecessaryto provide constant current transistors in series with the first andsecond ground side transistors. Consequently, the circuit constructioncan be simplified.

According to the write driver circuit of claim 10, in the write drivercircuit according to claim 5 or 6, first and second differentiatingcircuits for differentiating a write signal are provided at inputterminals of the fifth and sixth switching means.

With the construction, effects similar to those of the write drivercircuit according to claim 5 or 6 are produced. In addition, since thefirst and second differentiating circuits are provided at the inputterminals of the fifth and sixth switching means, the fifth and sixthswitching means can be completely turned off when the switching of thedirection of the write current is finished, and the current flowing tothe fifth and sixth switching means, that is, the current for decreasingthe base potentials of transistors does not flow, so that the currentconsumption can be further suppressed.

According to the write driver circuit of claim 11, in the write drivercircuit according to claim 4 or 7, third and fourth differentiatingcircuits for differentiating a write signal are provided at inputterminals of the seventh and eighth switching means.

With the construction, effects similar to those of claim 4 or 7 areproduced. In addition, by providing the third and fourth differentiatingcircuits at the input terminals of the seventh and eighth switchingmeans, the seventh and eighth switching means can be completely turnedoff upon completion of the switching of the direction of the writecurrent. Consequently, the current flowing to the seventh and eightswitching means, that is, the current to decrease the base potentials ofthe transistors does not flow, so that the current consumption can befurther suppressed.

According to the write driver circuit of claim 12, in the write drivercircuit according to claim 2 or 5, first and second clamp circuits forpreventing the first and second ground side transistors from beingsaturated are provided at the connecting point of the first power sourceside transistor and the first ground side transistor and the connectingpoint of the second power source side transistor and the second groundside transistor, respectively.

With the construction, effects similar to those of claim 2 or 5 areproduced. Moreover, since the voltage across the magnetic head isclamped by using the first and second clamp circuits, the first andsecond ground side transistors can be prevented from being saturated.

According to the write driver circuit of claim 13, in the write drivercircuit according to claim 2 or 5, first and second protective resistorsfor regulating a current passing to the first and second power sourceside transistors are provided between the first and second power sourceside transistors and the power input terminal, respectively.

With the construction, effects similar to those of claim 2 or 5 areproduced. Since the current passed to the first and second power sourceside transistors is regulated by using the first and second protectiveresistors, breakage or deterioration caused by increase in the currentto the first and second power source side transistors when the magnetichead comes into contact with a magnetic recording medium can beprevented.

According to the write driver circuit of claim 14, in the write drivercircuit according to claim 3 or 6, a booster circuit for widening avoltage difference between both terminals of the magnetic head isprovided between at least one of the first and second switching meansand the power input terminal.

With the construction, effects similar to those of claim 3 or 6 areproduced. Moreover, the voltage difference between both terminals of themagnetic head can be widened by the booster circuit, so that thedirection of the write current passing through the magnetic head can beswitched at a higher speed.

According to the write driver circuit of claim 15, in the write drivercircuit according to claim 3 or 6, a booster circuit for widening avoltage difference between both terminals of the magnetic head isprovided between either the first switching means and the first powersource transistor or the second switching means and the second powersource side transistor and the power input terminal.

With the construction, effects similar to those of claim 3 or 6 areproduced. Moreover, the voltage difference between both terminals of themagnetic head can be widened by the booster circuit more than the caseof claim 14 and the direction of the write current passing through themagnetic head can be switched at a higher speed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram showing a fundamental construction of awrite driver circuit of a first embodiment of the invention;

FIG. 2 is a circuit diagram showing a specific construction of the writedriver circuit of the first embodiment of the invention;

FIG. 3 is a block diagram showing a selector circuit of the firstembodiment;

FIG. 4 is a time chart illustrating write signal waveforms (a), headterminal potential waveforms (b) of the first embodiment, and headterminal potential waveforms (c) of a conventional technique;

FIG. 5 is a circuit diagram showing a write driver circuit of a secondembodiment;

FIG. 6 is a waveform chart showing write signals and control signals ofswitching means in the second embodiment;

FIG. 7 is a circuit diagram showing a write driver circuit of a thirdembodiment;

FIG. 8 is a circuit diagram showing a write driver circuit of a fourthembodiment; and

FIG. 9 is a circuit diagram showing a conventional write driver circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment)

The first embodiment of the invention will be described with referenceto FIGS. 1, 2, 3, and 4.

FIG. 1 is a circuit diagram showing a fundamental construction of awrite driver circuit of the first embodiment of the invention. As shownin FIG. 1, in the write driver circuit, the collectors of NPNtransistors Q1 and Q2 are connected to a power input terminal (Vcc), thecollector of an NPN transistor Q3 is connected to the emitter of the NPNtransistor Q1, the collector of an NPN transistor Q4 is connected to theemitter of the NPN transistor Q2, the emitter of the NPN transistor Q3is connected to the ground terminal via a resistor R8, and the emitterof the NPN transistor Q4 is connected to the ground terminal via aresistor R9. That is, in the circuit, the four NPN transistors Q1 to Q4construct an H-shaped bridge circuit. The NPN transistors Q1 and Q2correspond to first and second power source side transistors and the NPNtransistors Q3 and Q4 correspond to first and second ground sidetransistors.

In the circuit, each of the NPN transistors Q3 and Q4 functions as anoutput side circuit of a current mirror circuit, that is, a currentsource circuit. Each of the bases is connected to the base of thetransistor in a corresponding reference side circuit. The reference sidecircuit is omitted in the diagram.

Switching means SW1 is connected between the power input terminal (Vcc)and the base of the NPN transistor Q1, switching means SW2 is connectedbetween the power input terminal (Vcc) and the base of the NPNtransistor Q2, switching means SW3 is connected between the base of theNPN transistor Q1 and the ground terminal, switching means SW4 isconnected between the base of the NPN transistor Q2 and the groundterminal, switching means SW5 is connected between the base of the NPNtransistor Q3 and the ground terminal, and switching means SW6 isconnected between the base of the NPN transistor Q4 and the groundterminal. The switching means SW1 and SW2 correspond to the first andsecond switching means, the switching means SW3 and SW4 correspond tothe fifth and sixth switching means, and the switching means SW5 and SW6correspond to the third and fourth switching means.

The on/off state of each of the switching means SW1, SW2, SW3, SW4, SW5,and SW6 is controlled in accordance with the write signal.

In the write driver circuit, one (X) of the terminals of the magnetichead HD is connected to the connection point of the NPN transistors Q1and Q3 and the other terminal Y of the magnetic head HD is connected tothe connection point of the NPN transistors Q2 and Q4.

FIG. 2 is a circuit diagram showing a specific construction of the writedriver circuit of the first embodiment of the invention. The writedriver circuit is constructed as shown in FIG. 2. The connectingrelations of the NPN transistors Q1, Q2, Q3, and Q4, the resistors R8and R9, and the magnetic head HD are as described above with referenceto FIG. 1.

In the switching means SW1, the emitter of a PNP transistor Q5 isconnected to the power input terminal (Vcc), the collector of the PNPtransistor Q5 is connected to the base of the NPN transistor Q1, theemitter of a PNP transistor Q7 is connected to the base of the PNPtransistor Q5, and the collector of the PNP transistor Q7 is connectedto the ground terminal. A pull-up resistor R13 is connected between theemitter and base of the PNP transistor Q5, a pull-up resistor R1 isconnected between the emitter of the PNP transistor Q5 and the base ofthe PNP transistor Q7, a diode D1 is connected between the collector ofthe PNP transistor Q5 and the base of the PNP transistor Q7, and apull-down resistor R11 is connected between the base of the NPNtransistor Q1 and the ground terminal. The base of the PNP transistor Q7is provided with an input terminal TG1.

The switching means SW2 has a construction similar to that of theswitching means SW1 and comprises PNP transistors Q9 and Q11, pull-upresistors R4 and R14, pull-down resistor R12, and a diode D3. The baseof the PNP transistor Q11 is provided with an input terminal TG2.

The switching means SW3 is connected to the base of the NPN transistorQ1 via a resistor R3, the collector of an NPN transistor Q6 is connectedto the base of the NPN transistor Q1 via the resistor R3, and theemitter of the NPN transistor Q6 is connected to the ground terminal.The emitter of an NPN transistor Q8 is connected to the base of the NPNtransistor Q6 and the collector of the NPN transistor Q8 is connected tothe power input terminal (Vcc). A pull-down resistor R15 is connectedbetween the base of the NPN transistor Q6 and the ground terminal (thatis, the emitter of the NPN transistor Q6), a pull-down resistor R2 isconnected between the base of the NPN transistor Q8 and the groundterminal, and a diode D2 is connected between the base of the NPNtransistor Q8 and the collector of the NPN transistor Q6. The base ofthe NPN transistor Q8 is provided with an input terminal TG3.

The switching means SW4 has a construction similar to that of theswitching means SW3 and comprises NPN transistors Q10 and Q12, pull-downresistors R5 and R16, and a diode D4. The base of the NPN transistor Q12is provided with an input terminal TG4.

In the switching means SW5, the collector of an NPN transistor Q13 isconnected to the base of the NPN transistor Q3, the emitter of the NPNtransistor Q13 is connected to the ground terminal, the emitter of anNPN transistor Q14 is connected to the base of the NPN transistor Q13,and the collector of the NPN transistor Q14 is connected to the powerinput terminal (Vcc). A pull-down resistor R17 is connected between thebase of the NPN transistor Q13 and the ground terminal (that is, theemitter of the NPN transistor Q13), a pull-down resistor R7 is connectedbetween the base of the NPN transistor Q14 and the ground terminal, anda diode D5 is connected between the base of the NPN transistor Q14 andthe collector of the NPN transistor Q13. The base of the NPN transistorQ14 is provided with an input terminal TG5.

The switching means SW6 has a construction similar to that of theswitching means SW5 and comprises NPN transistors Q16 and Q17, pull-downresistors R10 and R18, and a diode D6. The base of the NPN transistorQ17 is provided with an input terminal TG6.

In the circuit of FIG. 2, besides the switching means SWl to SW6,switching means SW7 for controlling the switching means SW5 andswitching means SW8 for controlling the switching means SW6 areprovided. In the switching means SW7, the collector of an NPN transistorQ15 is connected to the base of the NPN transistor Q13, the emitter ofthe NPN transistor Q15 is connected to the ground terminal, and the baseof the NPN transistor Q15 is provided with an input terminal TG7. In theswitching means SW8, the collector of an NPN transistor Q18 is connectedto the base of the NPN transistor Q16, the emitter of the NPN transistorQ18 is connected to the ground terminal, and the base of the NPNtransistor Q18 is provided with an input terminal TG8. The switchingmeans SW7 and SW8 correspond to seventh and eighth switching means.

In the write driver circuit of the first embodiment, the switching meansSW1 is constructed by a Darlington circuit comprising the PNPtransistors Q5 and Q7, the resistors R1, R11, and R13, and the diode D1.The input terminal TG1 is connected to the base of the PNP transistorQ7, that is, the base of the Darlington circuit. The switching means SW3is constructed by a Darlington circuit comprising the NPN transistors Q6and Q8, the resistors R2 and R15, and the diode D2. The input terminalTG3 is connected to the base of the NPN transistor Q8, that is, the baseof the Darlington circuit. The base potential of the NPN transistor Q1is controlled by the switching means SW1 and SW3.

In a manner similar to the above construction, the switching means SW2is constructed by a Darlington circuit comprising the PNP transistors Q9and Q11, the resistors R4, R12, and R14, and the diode D3. The inputterminal TG2 is connected to the base of the PNP transistor Q11, thatis, the base of the Darlington circuit. The switching means SW4 isconstructed by a Darlington circuit comprising the NPN transistors Q10and Q12, the resistors R5 and R16, and the diode D4. The input terminalTG4 is connected to the base of the NPN transistor Q12, that is, thebase of the Darlington circuit. The base potential of the NPN transistorQ2 is controlled by the switching means SW2 and SW4.

Further, the switching means SW5 is constructed by a Darlington circuitcomprising the NPN transistors Q13 and Q14, the resistors R7 and R17,and the diode D5. The input terminal TG5 is connected to the base of theNPN transistor Q14, that is, the base of the Darlington circuit tocontrol the base potential of the transistor Q3.

The switching means SW6 is similarly constructed by a Darlington circuitcomprising the NPN transistors Q16 and Q17, the resistors R10 and R18,and the diode D6. The input terminal TG6 is connected to the base of theNPN transistor Q17, that is, the base of the Darlington circuit tocontrol the base potential of the NPN transistor Q4.

The switching means SW7 is constructed by the NPN transistor Q15, andthe input terminal TG7 and the base of the NPN transistor Q15 areconnected to control the base potential of the NPN transistor Q13,thereby controlling the switching means SW5. The switching means SW8 hasa similar construction and is constructed by the NPN transistor Q18 andthe input terminal TG8 and the base of the NPN transistor Q18 areconnected to control the base potential of the NPN transistor Q16,thereby controlling the switching means SW6.

In the above, the NPN transistors Q1 to Q4 and the switching means SW1,SW2, SW5, and SW6 construct a reversal switching circuit and theswitching means SW3 and SW4 construct high-speed reversing means forwidening the potential difference between both terminals of the magnetichead HD until the write current is reversed. The switching means SW7 andSW8 have the function of quickening the start-up upon energization ofthe switching means SW5 and SW6.

The switching means SW1, SW2, SW3, SW4, SW5, SW6, SW7, and SW8 arecontrolled by supplying control signals outputted from a selectorcircuit 1 shown in FIG. 3 to the input terminals TG1, TG2, TG3, TG4,TG5, TG6, TG7, and TG8 to turn on or off the NPN transistors Q1, Q2, Q3and Q4, thereby switching the direction of the write current passing tothe magnetic head HD.

In FIG. 3, WD and WDB are input terminals of the write signal, TG1, TG2,TG3, TG4, TG5, TG6, TG7, and TG8 are output terminals of controlsignals, and 1 denotes the selector circuit. When write signals oflogics which are opposite to each other are supplied to the inputterminals WD and WDB, the selector circuit 1 outputs the control signalsof the switching means SW1, SW2, SW3, SW4, SW5, SW6, SW7, and SW8satisfying the logic of a table of truth values of Table 1 to the outputterminals TG1, TG2, TG3, TG4, TG5, TG6, TG7, and TG8.

TABLE 1 TG1 TG2 TG3 TG4 TG5 TG6 TG7 TG8 WD H L H L H H L L H WDB L WD LH L H L L H H L WDB H

The output terminals TG1, TG2, TG3, TG4, TG5, TG6, TG7, and TG8 of theselector circuit 1 of FIG. 3 are the same as the input terminals TG1,TG2, TG3, TG4, TG5, TG6, TG7, and TG8 of the write driver circuit inFIG. 2, and the same reference numerals are used.

The operation of the write driver circuit constructed as mentioned abovewill now be mentioned as below. When a high-level write signal issupplied to the input terminal WD and a low-level write signal issupplied to the input terminal WDB, as shown in Table 1, high-levelcontrol signals of the switching means SW2, SW4, SW5, and SW8 aresupplied to the TG2, TG4, TG5, and TG8 and low-level control signals ofthe switching means SW1, SW3, SW6, and SW7 are supplied to the TG1, TG3,TG6, and TG7. By turning on the switching means SW2, SW4, SW5, and SW8and turning off the switching means SW1, SW3, SW6, and SW7, the NPNtransistors Q1 and Q4 are turned on, the NPN transistors Q2 and Q3 areturned off, and the write current is passed through the magnetic head HDin the direction from the terminal X to the terminal Y. The operation issimilarly performed also in the opposite case and the write current ispassed through the magnetic head HD in the direction from the terminal Yto the terminal X.

The operation in a period from the state of the upper section of Table 1to the state of the lower section, during which the write signalsupplied to the input terminal WD is changed from the high level to thelow level, the write signal supplied to the input terminal WDB ischanged from the low level to the high level, that is, the controlsignals applied to the input terminals TG1, TG3, TG6, and TG7 arechanged from L (low level) to H (high level), the control signalsapplied to the input terminals TG2, TG4, TG5, and TG8 are changed from Hto L as shown in Table 1, and the direction from the terminal X to theterminal Y of the write current passing through the magnetic head HD isreversed to the direction from the terminal Y to the terminal X will nowbe described. In the following description of the operation, withrespect to the control signals supplied to the input terminals TG1, TG2,TG3, TG4, TG5, TG6, TG7, and TG8, only the state after the change isdescribed.

When the control signal L is supplied to the input terminal TG2, theswitching means SW2 is turned on. When the control signal L is suppliedto the input terminal TG4, the switching means SW4 is turned off.Consequently, a base potential Vb2 of the NPN transistor Q2 starts tochange (rise) to a voltage which is dropped from the power sourcevoltage Vcc only by the voltage Vbe by the PNP transistors Q9 and Q11and the diode D3 constructing the switching means SW2, and the NPNtransistor Q2 is turned on.

The voltage Vbe denotes either a base-emitter voltage of the transistorconstructing any of the switching means SW1 to SW8 or a forward voltageof a diode and its value is about 0.7V. The base potential Vb2 of theNPN transistor Q2 becomes a voltage dropped from the power sourcevoltage Vcc only by the voltage Vbe for the following reason. When theswitching means SW2 is turned on, the potential at the input terminalTG2 is fixed to the voltage dropped from the power source voltage Vcconly by a voltage 2Vbe, and the base potential Vb2 of the NPN transistorQ2 becomes a voltage higher than the potential at the input terminal TG2only by a forward voltage of the diode D3. Since the switching means SW4is off at this time, it does not contribute to the base potential Vb2 ofthe NPN transistor Q2.

On the other hand, since control signals H are supplied to the inputterminals TG1 and TG3, the switching means SW1 is turned off and theswitching means SW3 is turned on. Consequently, a base potential Vb1 ofthe NPN transistor Q1 starts to change (drop) to the voltage Vbe by theNPN transistors Q6 and Q8 and the diode D2 constructing the switchingmeans SW3 and the NPN transistor Q1 is turned off. In this case, whenthe switching means SW1 is turned off, the switching means SW3 is turnedon, thereby enabling the base potential Vb1 of the NPN transistor Q1 tobe rapidly dropped as compared with the case where the base potentialVb1 of the NPN transistor Q1 is dropped only by the pull-down resistorR11. As described above, the base potential Vb1 of the NPN transistor Q1becomes the voltage Vbe for the following reason. When the switchingmeans SW3 is turned on, the potential at the input terminal TG3 is fixedto the voltage 2Vbe when the ground potential is a reference, and thebase potential Vb1 of the NPN transistor Q1 becomes a voltage lower thanthe potential of the input terminal TG3 only by the forward voltage ofthe diode D2. Since the switching means SW1 is off at this time, it doesnot contribute to the base potential Vb1 of the NPN transistor Q1.

Since the control signals L and H are supplied to the input terminalsTG5 and TG7, respectively, the switching means SW5 is turned off and theswitching means SW7 is turned on. A predetermined write current Iaccording to the current mirror reference side circuit flows, a basepotential Vb3 of the NPN transistor Q3 becomes a voltage obtained byadding the amount corresponding to the voltage drop by the resistor RBand the write current I and a base-emitter voltage Vbe3 of the NPNtransistor Q3, and the NPN transistor Q3 is turned on. Since theswitching means SW5 is off at this time, it does not contribute to thebase potential Vb3 of the NPN transistor Q3. When the switching meansSW7 is turned on, the base potential of the NPN transistor Q13 in theswitching means SW5 rapidly drops and the switching means SW5 is turnedoff quickly.

On the other hand, since the control signals H and L are supplied to theinput terminals TG6 and TG8, respectively, the switching means SW6 isturned on and the switching means SWB is turned off. A base potentialVb4 of the NPN transistor Q4 starts to change (drop) to the voltage Vbeby the NPN transistors Q16 and Q17 and the diode D6 constructing theswitching means SW6 and the NPN transistor Q4 is turned off. The basevoltage Vb4 of the NPN transistor Q4 becomes the voltage Vbe asdescribed above for the following reason. When the switching means SW6is turned on, the potential of the input terminal TG6 is fixed to thevoltage 2Vbe by using the ground potential as a reference and the basepotential Vb4 of the NPN transistor Q4 becomes a voltage lower than thepotential of the input terminal TG6 only by the amount of the forwardvoltage of the diode D6.

From the above, the voltage Vy at the terminal Y of the magnetic head HDbecomes a voltage dropped from the base potential Vb2 of the NPNtransistor Q2 only by the base-emitter voltage Vbe2 of the NPNtransistor Q2. When the power source voltage is Vcc, the voltageVy atthe terminal Y can be expressed by the following expression (5).

Vy=Vb2−Vbe2=Vcc−(Vbe+Vbe2)  (5)

The voltage Vx at the other terminal X of the magnetic head HD in astationary state after the direction of the write current is reversedbecomes a voltage dropped from the voltage Vy at the terminal Y of themagnetic head HD only by an amount of the voltage drop caused by theresistance component RH of the magnetic head HD and the write current Iand can be expressed by the following expression (6).

Vx=Vy−I·RH=Vcc−(Vbe+Vbe2)−I·RH  (6)

In a transient state until the direction of the write current isreversed, the NPN transistor Q2 starts to be turned on and the NPNtransistor Q1 starts to be turned off and the state is also consideredas a state where both of the NPN transistors Q1 and Q2 are ON. In thiscase, the voltage across the magnetic head HD is as follows. The voltageVy at the terminal Y is expressed by the following expression (7) in amanner similar to the stationary state.

Vy=Vcc−(Vbe+Vbe2)  (7)

The voltage Vx at the terminal X becomes the voltage dropped from thebase potential Vb1 of the NPN transistor Q1 only by the base-emittervoltage Vbe1 of the NPN transistor Q1 and is expressed by the followingexpression (8).

Vx=Vb1−Vbe1  (8)

At this time, the switching means SW1 is turned off and the switchingmeans SW3 is turned on, thereby passing a large current to the collectorof the NPN transistor Q6. Consequently, the base potential Vb1 of theNPN transistor Q1 is changing (dropping) rapidly to the voltage Vbe byusing the ground potential as a reference. The voltage Vx at theterminal X becomes a low voltage, so that the voltage differenceoccurring between both terminals of the magnetic head HD can be widenedand the direction of the write current passing through the magnetic headHD at a high speed can be rapidly reversed. When the reversal of thedirection of the write current is finished, the base potential Vb1 ofthe NPN transistor Q1 becomes a voltage increased from the groundpotential by the voltage Vbe by the turn-on of the switching means SW3.The NPN transistor Q6, that is, the switching means SW3 is turned offand the current passing to the collector of the NPN transistor Q6, thatis, the current passing to the switching means SW3 becomes smaller, sothat the current consumption becomes lower as compared with that of aconventional technique.

As mentioned above, since the decreasing speed of the base potential ofeach of the NPN transistors Q1 and Q2 is slow when only the pull-downresistors R11 and R12 are used, the switching means SW3 and SW4 areprovided to solve the problem. That is, although the base potentials ofthe NPN transistors Q1 and Q2 are reduced by the switching means SW1 andSW2 without the switching means SW3 and SW4, the switching means SW3 andSW4 are provided in order to decrease the base potential at a highspeed.

In the case where the write current changes in the direction opposite tothe above direction, the operation is similar to the above.

The point of controlling the switching means SW5 and SW6 by theswitching means SW7 and SW8 will now be described in detail. Forexample, by supplying the control signal H to the input terminal TG5,the switching means SW5 is turned on, the base potential Vb3 of the NPNtransistor Q3 becomes a voltage increased from the ground potential byan amount of Vbe, and the NPN transistor Q3 is turned off. On thecontrary, by supplying the control signal L to the input terminal TG5,the switching means SW5 is turned off, the base potential Vb3 of the NPNtransistor Q3 rises to a voltage obtained by adding the amount of thevoltage drop caused by the resistor R8 and the write current and thebase-emitter voltage Vbe3 of the NPN transistor Q3, and the NPNtransistor Q3 is turned on.

When the control signal L is supplied to the input terminal TG5, thepull-down resistors R7 and R17 pull down the base potential of the NPNtransistor Q14 and the base potential of the NPN transistor Q13 to theground potential so that the NPN transistors Q14 and Q13 are turned off,thereby turning off the switching means SW5. In the case where only thepull-down resistors R7 and R17 are used, however, a relatively long timeis necessary as time required to pull down the base potential of the NPNtransistor Q13 to the ground potential. In order to decrease the basepotential of the NPN transistor Q13 to the ground potential rapidly, theswitching means SW7, that is, the NPN transistor Q15 is provided betweenthe base of the NPN transistor Q13 and the ground terminal, therebyenabling the switching means SW5 to be rapidly turned off, that is,enabling the NPN transistor Q3 to be rapidly turned on. As a result, thewrite current can be reversed at a high speed. The operations of theswitching means SW6 and SW7 are similar to the above.

Description will be given with respect to the point that the NPNtransistors Q3 and Q4 are controlled in an active region by theswitching means SW5 to SW8. The base potentials of the NPN transistorsQ3 and Q4 are controlled by voltages of the levels shown below.

High level Vbe3+I·R8 or Vbe4+I·R9

Low level Vbe (voltage across the ground terminals of the switchingmeans SW5 and SW6)

The high-level and low-level voltages are set so that both of the NPNtransistors Q3 and Q4 can be used in the active region. At the time ofhigh level, a current of about tens mA is passed to the collectors ofthe NPN transistors Q3 and Q4. At the time of low level, a current offew mA or less is passed. A slight current (few mA or less) is passedalso at the OFF time for the reason described hereinbelow. To bespecific, with such a construction, as compared with a case where thelow level is the ground potential and the NPN transistors Q3 and Q4 arechanged to an interrupting region and are completely turned off so asnot to pass a current to the collectors, the ON/OFF state of the NPNtransistors Q3 and Q4, that is, whether the write current is led to thecollectors or not can be switched at a higher speed, and the writecurrent can be reversed at a higher speed also from this point.

As mentioned above, the switching means SW5 and SW6 are provided inorder to control the NPN transistors Q3 and Q4 in the active region andto turn on/off the current passing to the NPN transistors Q3 and Q4 at ahigh speed and are not used to directly widen the voltage differencebetween both terminals of the magnetic head HD. Since the NPNtransistors Q3 and Q4 serve as output transistors of the current mirror,however, the base potential of the NPN transistor Q3 becomes a voltageobtained by adding the base-emitter voltage Vbe3 and the amountcorresponding to the voltage drop caused by the resistor R8 and thewrite current and the base potential of the NPN transistor Q4 becomes avoltage obtained by adding the base-emitter voltage Vbe4 and the amountcorresponding to the voltage drop caused by the resistor R9 and thewrite current. Consequently, the base potential can be set to be lowerthan that of each of the NPN transistors Q23 and Q24 in the conventionalcircuit (refer to FIG. 9). This widens the voltage difference betweenthe terminals of the magnetic head HD. That is, since the base potentialof each of the NPN transistors Q3 and Q4 in the circuit of FIG. 1 can beset to be lower than the base potential of each of the NPN transistorsQ23 and Q24 in FIG. 9 only by an amount of the current source I1 in FIG.9, the voltage difference between the terminals of the magnetic head HDcan be widened.

FIG. 4 is a time chart of the circuit of FIG. 2, in which (a) shows thewaveforms of the write signals (WD, WDB), (b) shows the waveforms of thehead terminal potentials Vx and Vy at both terminals X and Y of themagnetic head HD in the first embodiment, and (c) illustrates thewaveforms of the head terminal potentials Vx and Vy at both terminals Xand Y of the conventional magnetic head HD. When the waveforms of (b)are compared with those of (c) in FIG. 4, it is obvious that thedifference between the head terminal potentials Vx and Vy at bothterminals X and Y of the magnetic head HD during the write current isreversed of the first embodiment is larger than that of the conventionaltechnique.

The first embodiment has the construction that the voltage differencebetween both terminals of the magnetic head HD is large during the writecurrent passing through the magnetic head HD is reversed. In this case,the switching means SWl to SW6 are connected to the bases of the NPNtransistors Q1 to Q4 and the switching means SW7 and SW8 for controllingthe switching means SW5 and SW6 are connected to the switching means SW5and SW6, respectively. Specifically, as switching means for controllingthe base voltage of the NPN transistor Q1, the switching means SW1 isconnected between the power input terminal and the base of the NPNtransistor Q1 and the switching means SW3 is connected between the baseof the NPN transistor Q1 and the ground terminal. As switching means forcontrolling the base voltage of the NPN transistor Q2, the switchingmeans SW2 is connected between the power input terminal and the base ofthe NPN transistor Q2 and the switching means SW4 is connected betweenthe base of the NPN transistor Q2 and the ground terminal. As switchingmeans for controlling the base voltage of the NPN transistor Q3, theswitching means SW5 is connected between the base of the NPN transistorQ3 and the ground terminal. As switching means for controlling the basevoltage of the NPN transistor Q4, the switching means SW5 is connectedbetween the base of the NPN transistor Q4 and the ground terminal. Asswitching means for controlling the switching means SW5, the NPNtransistor Q15 serving as the switching means SW7 is connected betweenthe base of the NPN transistor Q13 and the ground terminal. As switchingmeans for controlling the switching means SW6, the NPN transistor Q18serving as the switching means SW8 is connected between the base of theNPN transistor Q16 and the ground terminal.

The emitter of the NPN transistor Q1 and the collector of the NPNtransistor Q3 are connected to each other, the emitter of the NPNtransistor Q2 and the collector of the NPN transistor Q4 are connectedto each other, and the magnetic head HD is connected by using theconnecting point of the NPN transistors Q1 and Q3 and the connectingpoint of the NPN transistors Q2 and Q4 as first and second outputterminals. The switching means SW3 and SW4 make the base potentials ofthe NPN transistors Q1 and Q2 drop by the reversal of the write signalsWD and WDB during the write current passing through the magnetic head HDis reversed and the potential of the first or second output terminal isdecreased, thereby widening the voltage difference between bothterminals of the magnetic head HD.

According to the first embodiment, the H-shaped bridge circuit isconstructed by using the NPN transistors Q1, Q2, Q3, and Q4, theswitching means SW1 to SW4 for controlling the base potentials of theNPN transistors Q1 and Q2 are provided, the switching means SW5 to SW8for controlling the base potentials of the NPN transistors Q3 and Q4 areprovided, and the base potential of one of the NPN transistors Q1 andQ2, which is turned off is rapidly dropped by turning on the switchingmeans SW3 or SW4 which constructs high-speed reversing means.Consequently, the potential difference occurring between both terminalsof the magnetic head HD can be widened and the direction of the writecurrent passing through the magnetic head HD can be switched at a highspeed.

When the switching of the direction of the write current is finished,the base potential of the NPN transistor Q1 or Q2 becomes a low-levelvoltage and the current for dropping the base potential is not passed,thereby enabling the current consumption to be suppressed more than theconventional technique.

Since one of the switching means SW5 and SW6, which is turned off israpidly turned off by the switching means SW7 or SW8, one of the thirdand fourth NPN transistors Q3 and Q4, which is turned on can be rapidlyturned on and the reversal of the write current can be accordinglyhastened.

Since the NPN transistors Q3 and Q4 are controlled in the active regionand the current is not completely interrupted, the write current can bereversed at a high speed.

Since the NPN transistors Q3 and Q4 are constant current transistors, itis unnecessary to separately provide a constant current transistor andthe circuit construction can be simplified.

NMOS transistors may be used as the PNP transistors Q5 and Q9 and PMOStransistors may be used as Q6, Q10, Q13, Q15, Q16, and Q18 in theswitching means SW1, SW2, SW3, SW4, SW5, SW6, SW7, and SW8.

(Second Embodiment)

The second embodiment of the invention will be described with referenceto FIGS. 5 and 6. Specifically, according to the second embodiment, inthe write driver circuit of FIG. 2 of the first embodiment, adifferentiating circuit is added at the front stage of each of the inputterminals TG3, TG4, TG7, and TG8. A control signal outputted from theselector circuit 1 is differentiated and a resultant signal is applied.With such a construction, a differentiation signal obtained bydifferentiating the control signal outputted from the selector circuit 1is supplied to each of the input terminals TG3, TG4, TG7, and TG8. InFIG. 5, each of R19, R20, R21, and R22 denotes a resistor as a componentof a differentiating circuit and each of C1, C2, C3, and C4 indicates acapacitor as a component of a differentiating circuit.

TG3′ is an input terminal of a differentiating circuit constructed bythe resistor Rl9 and the capacitor C1, TG4′ is an input terminal of adifferentiating circuit constructed by the resistor R20 and thecapacitor C2, TG7′ is an input terminal of a differentiating circuitconstructed by the resistor R21 and the capacitor C3, and TG8′ is aninput terminal of a differentiating circuit constructed by the resistorR22 and the capacitor C4. Specifically, the resistor R19 and thecapacitor C1 are connected in series between the terminal TG3 and theinput terminal TG3′, the resistor R20 and the capacitor C2 are connectedin series between the terminal TG4 and the input terminal TG4′, theresistor R21 and the capacitor C3 are connected in series between theterminal TG7 and the input terminal TG7′, and the resistor R22 and thecapacitor C4 are connected in series between the terminal TG8 and theinput terminal TG8′. The other construction is similar to that of thefirst embodiment of FIG. 2. The input terminals TG3′, TG4′, TG7′, andTG8′ are connected to the selector circuit 1 shown in FIG. 3.

FIG. 6 shows signals supplied to the terminals TG3, TG4, TG7, and TG8and the input terminals TG3′, TG4′, TG7′, and TG8′ in the write drivercircuit constructed as mentioned above. Control signals supplied to theterminals TG3′ and TG4′ have rectangular waves of opposite phases andcontrol signals supplied to the terminals TG7′ and TG8′ also haverectangular waves of opposite phases. For example, the control signalsupplied to the terminal TG3′ is converted into a signal of an upwardspike shape by the differentiating circuit comprised of the resistor R19and the capacitor C1 as shown in FIG. 6 when the level is changed fromthe low level to the high level. The control signal is converted into adownward spike-shaped signal when the level is changed from the highlevel to the low level and the resultant signal is supplied to the inputterminal TG3 of the switching means SW3. Only the upward spike-shapedsignal obtained when the level is changed from the low level to the highlevel turns on the switching means SW3. The above is similarly performedwith respect to each of the input terminals TG4, TG7, and TG8.

When the NPN transistor Q1 or Q2 is turned off from the ON state, thatis, only when the write current passing through the magnetic head HD isreversed, by turning on the switching means SW3 or SW4, the basepotential of the NPN transistor Q1 or Q2 is dropped rapidly. The voltagedifference occurring between both terminals of the magnetic head HD canbe widened and the write current passing through the magnetic head HDcan be changed at a high speed. After changing the write current passingthrough the magnetic head HD, by turning off the switching means SW3 andSW4, a current is not passed to the switching means SW3 and SW4.

In case of turning on the NPN transistor Q3 or Q4 which is in the OFFstate, that is, only when the write current passing through the magnetichead HD is reversed, by turning on the switching means SW7 or SW8, theNPN transistor Q15 or Q18 of the switching means SW5 or SW6 is turnedoff rapidly. Consequently, by turning on the NPN transistor Q3 or Q4rapidly, the write current passing through the magnetic head HD can beswitched at a high speed. When the switching of the write currentpassing through the magnetic head HD is finished, by turning off theswitching means SW7 and SW8, no current is passed to the switching meansSW7 and SW8.

According to the second embodiment, by providing the differentialcircuit at the input of each of the switching means SW3, SW4, SW7, andSW8, only when the direction of the write current passing through themagnetic head HD is changed, the voltage difference occurring betweenboth terminals of the magnetic head HD is widened, thereby enabling thedirection of the write current to be changed at a high speed. When theswitching of the direction of the write current is finished, theswitching means SW3, SW4, SW7, and SW8 are completely turned off and nocurrent is passed. Thus, the current consumption can be suppressed morethan the first embodiment.

Although the differentiating circuits are provided for all of theswitching means SW3, SW4, SW7, and SW8 in the above embodiment, byproviding the differentiating circuits are provided for either theswitching means SW3 and SW4 or the switching means SW7 and SW8, thecurrent consumption can be suppressed to a certain degree.

(Third Embodiment)

The third embodiment of the invention will be described with referenceto FIG. 7. The third embodiment is obtained by adding protectiveresistors and clamp circuits to the write driver circuit of FIG. 2 ofthe first embodiment.

In FIG. 7, R23 and R24 are protective resistors, Q19 and Q20 are NPNtransistors as components of a clamp circuit, and Vref denotes a voltagesource. The protective resistor R23 is provided between the collector ofthe NPN transistor Q1 and the power input terminal. The protectiveresistor R24 is provided between the collector of the NPN transistor Q2and the power input terminal. The collectors of the NPN transistors Q19and Q20 are connected to the power input terminals, the bases areconnected to the power source Vref, the emitter of the NPN transistorQ19 and the collector (terminal X) of the NPN transistor Q3 areconnected to each other, and the emitter of the NPN transistor Q20 andthe collector (terminal Y) of the NPN transistor Q4 are connected toeach other. The other construction is similar to that of FIG. 2 of thefirst embodiment.

In the write driver circuit constructed as mentioned above, the NPNtransistors Q19 and Q20 form a clamp circuit. When a high-level writesignal is supplied to the input terminal WD and a low-level write signalis supplied to the input terminal WDB, that is, when the NPN transistorsQ1 and Q4 are ON and the NPN transistors Q2 and Q3 are OFF, the voltageVx at the terminal X is clamped by the NPN transistor Q19 to a voltagedropped from the voltage of the voltage source Vref only by thebase-emitter voltage Vbe of the NPN transistor Q19. On the contrary, acase where the low-level write signal is supplied to the input terminalWD and the high-level write signal is supplied to the input terminal WDBis similar to the above.

The voltage Vy at the terminal Y is clamped by the NPN transistor Q20 toa voltage dropped from the voltage of the voltage source Vref only bythe base-emitter voltage Vbe of the NPN transistor Q20.

When the voltage level of the power source Vref is set to a high-levelvoltage Vbh of the base potential of each of the NPN transistors Q3 andQ4 controlled by the switching means SW5, SW6, SW7, and SW8 and thebase-emitter voltage of the NPN transistors Q19 and Q20 is set to Vbe,by setting the voltage of the voltage source Vref as shown by thefollowing expression (9), the NPN transistors Q3 and Q4 can be preventedfrom being saturated.

Vref>Vbh+Vbe  (9)

In the third embodiment, in order to prevent the NPN transistors Q3 andQ4 in FIG. 7 from being saturated when the collector voltage becomeslower than the base voltage by a counter electromotive force caused bythe inductance of the magnetic head HD, the clamp circuit constructed bythe transistors Q19 and Q20 is provided. In order to explain the effectsof the clamp circuit, the demerits in the case where the transistors Q3and Q4 are saturated will be described hereinbelow. When the NPNtransistors Q3 and Q4 are saturated, problems such that the controloperation by the current mirror cannot be performed and a preset writecurrent is not passed to the collector of the NPN transistor Q3 or Q4occur. The NPN transistor Q3 or Q4 is saturated when the collectorpotential becomes smaller than the base potential. Since the case wherethe collector potential is smaller than the base potential occurs due tothe counter electromotive force of the inductance L of the magnetic headHD, the clamp circuit is provided in order to prevent this.

By providing the protective resistor R23 or R24, when a magneticrecording medium comes into contact with the magnetic head HD, thecurrent passing to the collector of the NPN transistor Q1 or Q2 can beregulated. The other construction is similar to the first embodiment.

According to the third embodiment, the voltages Vx and Vy at bothterminals X and Y of the magnetic head HD are clamped by the NPNtransistors Q19 and Q20, thereby the NPN transistors Q3 and Q4 can beprevented from being saturated. By providing the upper limit of thecurrent passing through the magnetic head HD by the protective resistorsR23 and R24, the NPN transistors Q1 and Q2 can be prevented from beingbroken or deteriorated.

(Fourth Embodiment)

The fourth embodiment of the invention will be described with referenceto FIG. 8. The fourth embodiment is obtained by adding a booster(step-up) circuit to the write driver circuit of FIG. 2 of the firstembodiment.

In FIG. 8, 2 denotes a booster circuit. In place of the power inputterminal, the output terminal of the booster circuit 2 is connected tothe resistors R1, R4, R13, and R14, the emitters of the PNP transistorsQ5 and Q9, and the collectors of the NPN transistors Q1 and Q2. Theother construction is similar to the first embodiment.

In the write driver circuit constructed as mentioned above, by settingthe potential of each of the resistors R1, R4, R13, and R14, theemitters of the PNP transistors Q5 and Q9, and the collectors of the NPNtransistors Q1 and Q2 to be higher than the power source voltage Vcc,for example, in a period during which the write current passing throughthe magnetic head HD is reversed from the direction from the terminal Xto the terminal Y to the direction from the terminal Y to the terminalX, the base potential Vb2 of the NPN transistor Q2 is higher as comparedwith that of the first embodiment. The voltage at the terminal Y of themagnetic head HD can be set high, the base potential Vb1 of the NPNtransistor Q1 is dropped to the voltage level same as that of the firstembodiment, and the potential at the terminal X of the magnetic head HDcan be decreased to the voltage level same as that of the firstembodiment. The voltage difference occurring between both terminals ofthe magnetic head HD can be therefore wider than that of the firstembodiment. With respect to the period as well, during which the writecurrent passing through the magnetic head HD is reversed from thedirection from the terminal Y to the terminal X to the direction fromthe terminal X to the terminal Y, the base potential Vb1 of the NPNtransistor Q1 is higher as compared with that of the first embodiment.In a manner similar to the above, the voltage difference occurringbetween both terminals of the magnetic head HD can be wider than that ofthe first embodiment. The other construction is similar to the firstembodiment.

According to the fourth embodiment, by setting the voltage applied toeach of the resistors R1, R4, R13, and R14, the emitters of the PNPtransistors Q5 and Q9, and the collectors of the NPN transistors Q1 andQ2 to be higher than the power source voltage, the write current passingthrough the magnetic head HD can be reversed at a higher speed ascompared with the first embodiment. Also with the construction in whichonly the switching means SW3 and SW4 are connected to the boostercircuit 2 and the collectors of the NPN transistors Q1 and Q2 areconnected to the power input terminal, the booster function is obtained.As compared with the case of using no booster circuit 2, the voltagedifference between both terminals X and Y of the magnetic head HD can bemade wider and the direction of the write current passing through themagnetic head HD can be switched at a higher speed. In this case, underthe condition that the power voltage is increased to a degree at whichthe base potential of each of the NPN transistors Q1 and Q2 determinedby the switching means SW3 and SW4 does not become higher than the powervoltage (so as not to saturate the NPN transistors Q1 and Q2), theeffects of boost can be obtained.

In the case where the npn transistors Q1 and Q2 are connected to thebooster circuit 2 as mentioned above, there is no such regulation.

What is claimed is:
 1. A write driver circuit comprising: a reversalswitching circuit having a pair of output terminals connected to bothterminals of a magnetic head, for reversing the direction of a writecurrent passing through the magnetic head in response to reversal of awrite signal, and reversing means for reversing the write current bymaking a voltage difference between both terminals of the magnetic headin a period from reversal of the write signal to reversal of the writecurrent to the magnetic head larger than a voltage difference betweenboth terminals of the magnetic head, which occurs only in the reversalswitching circuit, characterized in that the reversal switching circuitcomprises: a first power source side transistor and a first ground sidetransistor which are connected in series in the forward directionbetween a power input terminal and a ground terminal; a second powersource side transistor and a second ground side transistor which areconnected in series in the forward direction between the power inputterminal and the ground terminal; first switching means which isconnected to the base of the first power source side transistor inresponse to a write signal; second switching means which is connected tothe base of the second power source side transistor and controls thesecond power source side transistor in response to the write signal;third switching means which is connected to the base of the first groundside transistor and controls the first ground side transistor inresponse to the write signal; and fourth switching means which isconnected to the base of the second ground side transistor and controlsthe second ground side transistor in response to the write signal, themagnetic head is connected between a connecting point of the first powersource side transistor and the first ground side transistor and aconnecting point of the second power source side transistor and thesecond ground side transistor, and the operation of a set of the firstand fourth switching means and that of a set of the second and thirdswitching means are reversed in response to reversal of the write signalto reverse the operation of a set of the first power source sidetransistor and the second ground side transistor and that of a set ofthe second power source side transistor and the first ground sidetransistor, thereby reversing the write current passing through themagnetic head.
 2. The write driver circuit according to claim 1,characterized in that each of the first and second power source sidetransistors and the first and second ground side transistors is an NPNtransistor, the first switching means is connected between a power inputterminal and the base of the first power source side transistor, thesecond switching means is connected between the power input terminal andthe base of the second power source side transistor, the third switchingmeans is connected between the base of the first ground side transistorand the ground terminal, and the fourth switch is connected between thebase of the second ground side transistor and the ground terminal. 3.The write driver circuit according to claim 2, characterized in that thethird switching means has a first NPN switch transistor whose collectoris connected to the base of the first ground side transistor and whoseemitter is connected to the ground terminal, the fourth switching meanshas a second NPN switch transistor whose collector is connected to thebase of the second ground side transistor and whose emitter is connectedto the ground terminal, seventh switching means for rapidly decreasingthe base potential of the first NPN switch transistor is providedbetween the base of the first NPN switch transistor and the groundterminal, and eighth switching means for rapidly decreasing the basepotential of the second NPN switch transistor is provided between thebase of the second NPN switch transistor and the ground terminal.
 4. Thewrite driver circuit according to claim 1, characterized in that thereversal switching circuit comprises: a first power source sidetransistor and a first ground side transistor which are connected inseries in the forward direction between a power input terminal and aground terminal; a second power source side transistor and a secondground side transistor which are connected in series in the forwarddirection between the power input terminal and the ground terminal;first switching means which is connected to the base of the first powersource side transistor and controls the first power source sidetransistor in response to a write signal; second switching means whichis connected to the base of the second power source side transistor andcontrols the second power source side transistor in response to thewrite signal; third switching means which is connected to the base ofthe first ground side transistor and controls the first ground sidetransistor in response to the write signal; and fourth switching meanswhich is connected to the base of the second ground side transistor andcontrols the second ground side transistor in response to the writesignal, wherein the magnetic head is connected between a connectingpoint of the first power source side transistor and the first groundside transistor and a connecting point of the second power source sidetransistor and the second ground side transistor, and the operation of aset of the first power source side transistor and the second ground sidetransistor and that of a set of the second power source side transistorand the first ground side transistor are reversed by reversing theoperation of a set of the first and fourth switching means and that of aset of the second and third switching means in response to reversal ofthe write signal, thereby reversing the write current passing throughthe magnetic head, said reversing means comprises fifth and sixthswitching means connected to the bases of the first and second powersource side transistors, the base potential of one of the first andsecond power source side transistors, which is turned off by thereversal of the write signal is selectively decreased to about theground potential and the potential at the connecting point of one of thepower source side transistors, which is turned off by the reversal ofthe write signal and the ground side transistor which is seriallyconnected to the power source side transistor is decreased, therebywidening the voltage difference between both terminals of the magnetichead.
 5. The write driver circuit according to claim 4, characterized inthat each of the first and second power source side transistors and thefirst and second ground side transistors is an NPN transistor, the firstswitching means is connected between a power input terminal and the baseof the first power source side transistor, the second switching means isconnected between the power input terminal and the base of the secondpower source side transistor, the third switching means is connectedbetween the base of the first ground side transistor and the groundterminal, the fourth switch is connected between the base of the secondground side transistor and the ground terminal, the fifth switchingmeans is connected between the base os the first power source sidetransistor and the ground terminal, and the sixth switching means isconnected between the base of the second power source side transistorand the ground terminal.
 6. The write driver circuit according to claim5, characterized in that the third switching means has a first NPNswitch transistor whose collector is connected to the base of the firstground side transistor and whose emitter is connected to the groundterminal; the fourth switching means has a second NPN switch transistorwhose collector is connected to the base of the second ground sidetransistor and whose emitter is connected to the ground terminal;seventh switching means for rapidly decreasing the base potential of thefirst NPN switch transistor is provided between the base of the firstNPN switch transistor and the ground terminal; and eighth switchingmeans for rapidly decreasing the base potential of the second NPN switchtransistor is provided between the base of the second NPN switchtransistor and the ground terminal.
 7. The write driver circuitaccording to claim 1, 2, 3, 4, 5 or 6, characterized in that the thirdand fourth switching means control the first and second ground sidetransistors within active regions, respectively.
 8. The write drivercircuit according to claim 1, 2, 3, 4, 5 or 6, characterized in thateach of the first and second ground side transistors is an output sidetransistor of a current mirror circuit.
 9. The write driver circuitaccording to claim 4 or 5, characterized in that first and seconddifferentiating circuits for differentiating a write signal are providedat input terminals of the fifth and sixth switching means.
 10. The writedriver circuit according to claim 3 or 6, characterized in that thirdand fourth differentiating circuits for differentiating a write signalare provided at input terminals of the seventh and eighth switchingmeans.
 11. The write driver circuit according to claim 1 or 4,characterized in that first and second clamp circuits for preventing thefirst and second ground side transistors from being saturated areprovided at the connecting point of the first power source sidetransistor and the first ground side transistor and the connecting pointof the second power source side transistor and the second ground sidetransistor, respectively.
 12. The write driver circuit according toclaim 1 or 4, characterized in that first and second protectiveresistors for regulating a current passing to the first and second powersource side transistors are provided between the first and second powersource side transistors and the power input terminal, respectively. 13.The write driver circuit according to claim 2 or 5, characterized inthat a booster circuit for widening a voltage difference between bothterminals of the magnetic head is provided between the first and secondswitching means and the power input terminal.
 14. The write drivercircuit according to claim 2 or 5, characterized in that a boostercircuit for widening a voltage difference between both terminals of themagnetic head is provided between the first and second switching meansand the first and second power source side transistors and the powerinput terminal.